This invention relates to a charge-coupled device for use in solid image pickup devices, delay devices, memory devices, or the like and more particularly, to a buried channel charge-coupled device. Still more particularly, this invention relates to a buried channel charge-coupled device which includes an enhancement type, surface channel, field effect transistor for resetting a floating diffusion region to a predetermined potential.
Such buried channel charge-coupled devices are well known in the art. For example, at page 47 in an article entitled "Charge Transfer Device", published 1978 by Kidai Kagaku Sha, there is described a charge-coupled device used in a floating diffusion amplifier for use as a signal charge detecting circuit which comprises a semiconductor substrate, a buried channel formed on the substrate, and an output circuit comprised of a floating diffusion region. Clock pulse voltages are applied to respective transfer gate electrodes so as to transfer a signal charge through the transfer channel. An output gate is connected to supply the transferred signal charge into the floating diffusion region. A charge sensing circuit senses the voltage level of the floating diffusion region. The floating diffusion region is also a part of a precharge transistor which periodically resets the floating diffusion region to a predetermined potential in response to a reset pulse voltage signal.
In such conventional buried channel charge-coupled devices, however, the precharge transistor has been provided in the form of a buried channel MOSFET which can only be driven by a reset pulse signal having a relatively great amplitude. In order to drive the precharge transistor in response to the output of a digital timing generator, therefore, a driver circuit is required to boost the reset pulse voltage signal outputted from the digital timing generator.
Accordingly, it is a problem with such a floating diffusion amplifier to provide a charge-coupled device which includes a charge sensing circuit that can be reset with a lower reset pulse voltage without a driver circuit for amplifying the pulse reset signals from a digital timing source.